The present invention relates generally to multi-processor computer systems. A relatively new approach to the design of multi-processor systems replaces broadcast communication such as bus or ring architectures among processors with a point-to-point data transfer mechanism in which the processors communicate similarly to network nodes in a tightly-coupled computing system. That is, the processors are interconnected via a plurality of communication links and requests are transferred among the processors over the links according to routing tables associated with each processor. The intent is to increase the amount of information transmitted within a multi-processor platform per unit time.
In some multi-processor systems, local nodes (including processors, input/output (I/O) devices, etc.) are directly connected to each other through a plurality of point-to-point intra-cluster links to form a cluster of two or more processors. The point-to-point links significantly increase the bandwidth for coprocessing and multiprocessing functions.
However, it is sometimes desirable to eliminate one or more of the processors in a cluster designed for multiple processors. For example, some customers will not require the processing capabilities of all processors and may prefer a lower-cost machine having fewer processors. Such customers will generally want to maintain all of the I/O capability of a machine with a full complement of processors. Therefore, it would be desirable to provide techniques for reducing the number of processors on a motherboard designed to accommodate multiple processors, while maintaining most or all of the input/output capability of the original design.